The present invention relates to a method of fabricating semiconductor structures and, more particularly, to a method of enhancing semiconductor device performance by modulating spacer induced stress.
Minimum feature sizes of CMOS semiconductor devices are continuously being reduced. To overcome limitations of the scaling of CMOS devices various techniques have been developed to enhance carrier mobility. One such technique is to induce stress in the channel region to enhance carrier mobility. Various ways to induce stress in the channel region have been developed including: stress engineering through local strain techniques such as dual stress liners (DSL), and stress proximity technique (SPT); process induced strain methods such as stress memorization technique (SMT); and recessed SiGe source/drain for PMOS.
The SPT and DSL techniques have been demonstrated to improve both NFET and PFET drive currents. The reduced proximity of stress liner due to the removal of the spacer before the DSL process maximizes the strain transfer from nitride liner to the channel.
In the SMT process, the stress effect from the highly tensile nitride cap layer is enhanced and memorized by well-controlled poly gate amorphization and re-crystallization steps.
U.S. Pat. No. 6,975,006 to Huang et al. discloses the use of recessed first and second recessed spacers situated on top of first and second poly gate sidewall liners respectively. The height of the originally formed spacers is reduced for the recessed spacers. Also, the width of the horizontal part of the sidewall liner is shorter than the width of the spacer. It is asserted that the reduced spacer height can reduce the device channel stress.
U.S. Pat. No. 7,132,704 to Grudowski discloses the use of a tensile nitride spacer to enhance the NFET device performance. The stress in the tensile nitride spacers film can be adjusted with selectively or non-selective implantation of xenon or germanium either before or after etching the spacer film.
One disadvantage with prior techniques for modulating stress induced in the channel region is that they are relatively complex. Another disadvantage is that there is currently no simple technique, to the inventors' knowledge, to separately modulate the stress on various devices of different threshold voltages, such as for low, regular and high threshold voltages (LVT, RVT and HVT respectively). Another disadvantage with prior stress modulating techniques is that they cannot always be used in combination with other such techniques.
As can be seen, there is a need for an improved method of modulating spacer induced stress for device enhancement. Further, there is a need for such a technique which is not complex and with can allow the separate modulation of stress on various devices of different threshold voltages. Also, there is a need for a stress modulation technique that can be used in combination with other stress modulation techniques.